For the solution of electrosta雨男tic discharge problem了劇s, according to the foll農資owing twelve rules to (prioritize)
1.PCB non insul從好ated casing wire and other wire dist拿火ance of at least 化遠2.2 mm. This applies to all objec些醫ts connected to the chas紙商sis ground, including trajectory.知兵
2 chassis wire leng一請th should not be m習在ore than five ti綠內mes its width.
Metal objects 3 the circuit without i南靜nsulation and the operator些子 can touch to the PCB area or ungrou筆舞nded separated by at le弟子ast 2 cm.
4 power line and ground wire or 跳小ranking on PCB and i湖黑n the same layer, or place低動d adjacent to the two layer.
5 the ground plane and gr體得ound wire must be connecte懂黃d to the network. In an arbitra個場ry direction, at lea她放st 6 cm every connection a ver用和tical line and horizontal line. Especi是相ally the double PCB plate那花, that is to say,一綠 the first layer PCB board layout東資 can be ground level, and the second市費 layer can be v村紙ertical ground, must be at least ever西要y 6 centimeters place 綠吧a hole has been conne理綠cted to both (of course, less than 6 風鐵cm in the local connection is better機遠 than the ground grid, gro公少und plane.
) 6 of all signal lines mu市店st be in the ground pl煙術ane edges or less than 13 mm abov愛間e the ground. Wire can be distribut區業ed in the same laye少購r signal line, also can be in th地樂e next layer. If the signal li風下ne length of 30 cm從學 or more, it must b樹為e placed on a ground beside it, plac行城ed above the signal line了錢 or the adjacent surface of the gr你機ound can be.
Across the bypass capacitor between t暗不he 7 power line and the ground wire爸藍, the distance between each other音工 is not greater than 8 cm (so 但雨that each piece of integrated block may相得 have multiple byp離子ass capacitor is conne器會cted).
8 mutual connection more components在弟 rely on together.
All 9 components must be as close錢短 as possible to the I/O connecto森村r (Note: should m街北eet third).
The 10 part will spare all of P愛物CB filled with ground (atten雪紙tion should be paid to e湖市very 6 centimeters place continuou新河sly to produce ground netwo朋動rk).
11 if possible, wh問是ich will feed power line or signal學地 line from the edge at the center of P雪店CB board, and not from 聽章a corner out.
12 for the signal line is particularly 作樹sensitive and long (鐵年30 cm or longer), should be a哥國t regular intervals a金和nd ground.
Note: these design rules must be 有近applied to all 吃商PCB in the system (such as main boar劇光d and plug in the above board). For他鄉 example, when the applic哥照ation of article計短 second, a ground length including水明 the motherboard and the還讀 daughter board and the len鄉吧gth of all the earth.報山
1.PCB non insul從好ated casing wire and other wire dist拿火ance of at least 化遠2.2 mm. This applies to all objec些醫ts connected to the chas紙商sis ground, including trajectory.知兵
2 chassis wire leng一請th should not be m習在ore than five ti綠內mes its width.
Metal objects 3 the circuit without i南靜nsulation and the operator些子 can touch to the PCB area or ungrou筆舞nded separated by at le弟子ast 2 cm.
4 power line and ground wire or 跳小ranking on PCB and i湖黑n the same layer, or place低動d adjacent to the two layer.
5 the ground plane and gr體得ound wire must be connecte懂黃d to the network. In an arbitra個場ry direction, at lea她放st 6 cm every connection a ver用和tical line and horizontal line. Especi是相ally the double PCB plate那花, that is to say,一綠 the first layer PCB board layout東資 can be ground level, and the second市費 layer can be v村紙ertical ground, must be at least ever西要y 6 centimeters place 綠吧a hole has been conne理綠cted to both (of course, less than 6 風鐵cm in the local connection is better機遠 than the ground grid, gro公少und plane.
) 6 of all signal lines mu市店st be in the ground pl煙術ane edges or less than 13 mm abov愛間e the ground. Wire can be distribut區業ed in the same laye少購r signal line, also can be in th地樂e next layer. If the signal li風下ne length of 30 cm從學 or more, it must b樹為e placed on a ground beside it, plac行城ed above the signal line了錢 or the adjacent surface of the gr你機ound can be.
Across the bypass capacitor between t暗不he 7 power line and the ground wire爸藍, the distance between each other音工 is not greater than 8 cm (so 但雨that each piece of integrated block may相得 have multiple byp離子ass capacitor is conne器會cted).
8 mutual connection more components在弟 rely on together.
All 9 components must be as close錢短 as possible to the I/O connecto森村r (Note: should m街北eet third).
The 10 part will spare all of P愛物CB filled with ground (atten雪紙tion should be paid to e湖市very 6 centimeters place continuou新河sly to produce ground netwo朋動rk).
11 if possible, wh問是ich will feed power line or signal學地 line from the edge at the center of P雪店CB board, and not from 聽章a corner out.
12 for the signal line is particularly 作樹sensitive and long (鐵年30 cm or longer), should be a哥國t regular intervals a金和nd ground.
Note: these design rules must be 有近applied to all 吃商PCB in the system (such as main boar劇光d and plug in the above board). For他鄉 example, when the applic哥照ation of article計短 second, a ground length including水明 the motherboard and the還讀 daughter board and the len鄉吧gth of all the earth.報山
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